1. Field of the invention
The invention concerns data transmission, in the telecommunications field, in accordance with the ISO standard protocol, and more particularly in accordance with levels 1 and 2 of the standard.
The invention is more particularly concerned with a system for receiving and processing HDLC frames on a time division multiplex PCM type link, especially for a data switch.
2. Description of the prior art
The specific implementation behind the development of the invention concerns an HDLC (High-level Data Link Control) transmitter/receiver with 32 channels multiplexed onto a PCM link and integrated into a PCM controller associated with a data switch, for example.
However, the invention encompasses other implementations in which an ISO level 2 frame format (in place of the HDLC format) is combined with multiplexing of multiple formatted channels onto the transmission link (in place of the PCM technique).
HDLC encoding entails serializing the data and formatting it into successive identifiable frames each comprising, in particular, a frame separator signal (or "flag") and a frame validation indication on two bytes (signature based on the bits of the frame) that is recomputed at the receiving end.
The PCM transmission technique time-division multiplexes N independent logical channels onto a single physical transmission line in the form of PCM frames each identified by a PCM frame start/end byte. Within each PCM frame each channel is reserved the same byte of predetermined rank.
The insertion of the HDLC frames into the PCM format at the transmitting end and then the recovery of the frames at the receiving end presupposes the provision of a specific system at each end of the transmission system. The invention concerns the receive part of a system of this kind.
There are already known systems for receiving HDLC frames transmitted on PCM type channels comprising either a dedicated machine based on slice processors or a plurality of processors each assigned to one channel of the PCM link. In the known system shown in FIG. 4 the HDLC frames are recovered channel by channel after demultiplexing at 45. This is effected by means of a specific line for each of the channels comprising a dedicated HDLC circuit 41 and a dedicated processor 42 associated with a buffer memory 43. Each of the lines 44 corresponding to a separate channel feeds a common remultiplexer memory 47 which concentrates the decoded frames 48 before they are sent over a processing bus 50 with processors 49 of ISO level 3. The processor 42 analyzes the byte and/or status signals supplied by the circuit 41. Knowing the transmission system used (CCITT No 7, X.25 or other protocol) and maintaining an up to date progress indication, the processor 42 is responsible for processing messages received, that is to say for determining for each byte received the operation that reception of the byte is to initiate; it accomplishes this operation by communicating as necessary with other processors involved.
This existing system is fully operational but has the disadvantages of a large number of components (one component for each channel) and the resulting complexity of management.
These disadvantages are particularly constricting in developing switching systems for a very large number of lines carrying large amounts of digital data. Until recently, 32-channel PCM links carried a limited number of logical channels (two, for example), the other channels being analog channels. It was therefore feasible, and sometimes essential, to process each channel separately, the multiplication of the components 41, 42, 43 on just a few parallel channels being compensated by the resulting flexibility of configuration.
There are now being developed PCM type transmit/receive systems comprising only digital channels. For example, the signalling transfer points (STP) designed to be installed on the French public switched telephone network require a processing capacity in the order of 500 64 kbit/s HDLC channels.
The increasing digitization of the network and rising data signalling rates are now making it possible to introduce services offering increasingly superior performance (ISDN) and represent a clear requirement for better performance PCM/HDLC systems.
In this line of thinking, it is known to implement the functions of the circuit 41 for multiple time-division multiplexed channels using a single multiplexed circuit having a channel status memory; on reception of a byte of each channel in a frame, the state of the channel (memorized in the previous frame) is read in this memory in order to resume processing of the channel where it left off, after reception of a byte of this channel in the previous frame.
In comparison with the FIG. 4 diagram, a single multiplexed HDLC circuit of this kind would be provided on the input side of the demultiplexer 45, rather than there being one such circuit for each channel on the output side of the demultiplexer. It would therefore be necessary to use the same number of processors 42 and memories 43 as there are channels, in order to meet requirements concerning the analysis and processing of received frames and messages that they contain.
One objective of the invention is to provide a system for receiving HDLC frames transmitted on PCM channels comprising means common to all the channels for analyzing and processing frames in order to avoid the proliferation of identical hardware means for each channel whilst allowing for the fact that each frame must undergo specific processing.
Another objective of the invention is to provide a frame receiving and processing system of this kind which, when associated with a standard processor, makes it possible to reduce the time to execute repetitive frame analysis tasks.
Another objective of the invention is to provide a system of this kind enabling variable duration processing of the received data. A further objective of the invention is to provide, for a system of this kind, a fast, simple design, hardwired device compatible with simultaneous coexistence of different protocols (for "25 example, CCITT No 7 and X.25) on the PCM channels.